ARDFEN=ARDFEN_0, SERCLKDIV=SERCLKDIV_0, SCKFREERUNEN=SCKFREERUNEN_0, ATDFEN=ATDFEN_0, HSEN=HSEN_0, DOZEEN=DOZEEN_0, RXCLKSRC=RXCLKSRC_0, COMBINATIONEN=COMBINATIONEN_0
Module Control Register 0
| SWRESET | Software Reset |
| MDIS | Module Disable |
| RXCLKSRC | Sample Clock source selection for Flash Reading 0 (RXCLKSRC_0): Dummy Read strobe generated by FlexSPI Controller and loopback internally. 1 (RXCLKSRC_1): Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad. 3 (RXCLKSRC_3): Flash provided Read strobe and input from DQS pad |
| ARDFEN | Enable AHB bus Read Access to IP RX FIFO. 0 (ARDFEN_0): IP RX FIFO should be read by IP Bus. AHB Bus read access to IP RX FIFO memory space will get bus error response. 1 (ARDFEN_1): IP RX FIFO should be read by AHB Bus. IP Bus read access to IP RX FIFO memory space will always return data zero but no bus error response. |
| ATDFEN | Enable AHB bus Write Access to IP TX FIFO. 0 (ATDFEN_0): IP TX FIFO should be written by IP Bus. AHB Bus write access to IP TX FIFO memory space will get bus error response. 1 (ATDFEN_1): IP TX FIFO should be written by AHB Bus. IP Bus write access to IP TX FIFO memory space will be ignored but no bus error response. |
| SERCLKDIV | The serial root clock could be divided inside FlexSPI . Refer Clocks chapter for more details on clocking. 0 (SERCLKDIV_0): Divided by 1 1 (SERCLKDIV_1): Divided by 2 2 (SERCLKDIV_2): Divided by 3 3 (SERCLKDIV_3): Divided by 4 4 (SERCLKDIV_4): Divided by 5 5 (SERCLKDIV_5): Divided by 6 6 (SERCLKDIV_6): Divided by 7 7 (SERCLKDIV_7): Divided by 8 |
| HSEN | Half Speed Serial Flash access Enable. 0 (HSEN_0): Disable divide by 2 of serial flash clock for half speed commands. 1 (HSEN_1): Enable divide by 2 of serial flash clock for half speed commands. |
| DOZEEN | Doze mode enable bit 0 (DOZEEN_0): Doze mode support disabled. AHB clock and serial clock will not be gated off when there is doze mode request from system. 1 (DOZEEN_1): Doze mode support enabled. AHB clock and serial clock will be gated off when there is doze mode request from system. |
| COMBINATIONEN | This bit is to support Flash Octal mode access by combining Port A and B Data pins (A_DATA[3:0] and B_DATA[3:0]). 0 (COMBINATIONEN_0): Disable. 1 (COMBINATIONEN_1): Enable. |
| SCKFREERUNEN | This bit is used to force SCLK output free-running. For FPGA applications, external device may use SCLK as reference clock to its internal PLL. If SCLK free-running is enabled, data sampling with loopback clock from SCLK pad is not supported (MCR0[RXCLKSRC]=2). 0 (SCKFREERUNEN_0): Disable. 1 (SCKFREERUNEN_1): Enable. |
| IPGRANTWAIT | Time out wait cycle for IP command grant. |
| AHBGRANTWAIT | Timeout wait cycle for AHB command grant. |